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Silicon Physical Design Methodology Engineer

Location: Bangalore
Company: Google
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Minimum qualifications:
- 10 years of experience with ASIC design implementation and convergence
- Experience with block implementation and sign-off design flows
- Experience scripting in TCL, Perl, or Python
Preferred qualifications:
- Advanced degree in Electrical Engineering or Computer Science, with 5 years of related experience
- Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape outs and shipping silicon
- Experience evaluating multiple vendor solutions and driving tool decisions
- Experience delivering Product Privacy Assessment (PPA) objectives across projects
- Knowledge of technology node across foundries
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
As a Silicon Physical Design Methodology Lead, you will be responsible for architecture and developing industry-leading hierarchical implementation and sign-off flows and methodologies for System-on-Chip (SOC). In this role, you will work directly with design and Electronic Design Automation (EDA) teams to develop methodologies and flows to enable Application Specific Integrated Circuits (ASIC) implementation and verification that can scale across multiple projects and technology nodes. You will also help drive hierarchical methodology across different sign-off domains to deliver an end-to-end solution for all hierarchical blocks.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
- Lead architecture and development of all aspects of ASIC implementation methodologies with an emphasis on physical synthesis, design for testability, place and route, static timing analysis, third-party IP integration, DVFS, and advanced technology nodes.
- Collaborate with chip design teams to implement tools and methodologies to improve Power, Performance, and Area.
- Collaborate with Electrodermal Activity (EDA) vendors to deliver effective solutions for products.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.
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